#include "spi_io.h"
#include "axis_pci.h"
#include "axis.h"
Include dependency graph for spi_io.c:

Functions | |
| void | init_spi_channel (struct spi_channel *ptr,unsigned char no, struct axis_pci_device_entry *device) |
| Initialise a SPI channel structure. | |
| void | init_spi (struct axis_pci_device_entry *device) |
| int | wait_for_spi_free (struct spi_op *op) |
| moves spi operation on to queue for SPI hardware | |
| void | set_spi_control_1 (struct axis_pci_device_entry *device, unsigned char options) |
| Writes optional SPI settings (bitorder divisor clock phase etc) to control register. | |
| unsigned char | read_spi_status (struct axis_pci_device_entry *device) |
| Reads SPI status register. | |
| unsigned char | read_spi_control_1 (struct axis_pci_device_entry *device) |
| reads SPI control register 1 | |
| void | set_spi_control_2 (struct axis_pci_device_entry *device) |
| writes SPI control register 2 | |
| void | set_spi_address (struct axis_pci_device_entry *device, unsigned char address) |
| set up SPI addressing for selected channel | |
| void | disable_spi (struct axis_pci_device_entry *device) |
| turn off SPI | |
| int | despatch_spi_op (struct spi_op *op) |
| process a single SPI operation | |
| ssize_t | axis_spi_read (struct file *file_ptr, char *buffer, size_t size, loff_t *offset) |
| Gets data from the selected SPI and returns it to userland. | |
| ssize_t | axis_spi_write (struct file *file_ptr, const char *buffer,size_t size,loff_t *offset) |
| Copies data from USER space and sends it to spi. | |
| int | axis_spi_ioctl (struct inode *inode_ptr, struct file *file_ptr, unsigned int type,unsigned long args) |
| Provides an interface to allow user land to control spi options. | |
| int | axis_spi_open (struct inode *inode_ptr, struct file *file_ptr) |
| open function for spi support | |
| int | axis_spi_release (struct inode *inode_ptr, struct file *file_ptr) |
| Called by kernel in response to a process closing a device. | |
Variables | |
| file_operations | spi_file_operations |
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Provides an interface to allow user land to control spi options.
To allow user applications options other then read / write the driver support IOCTL calls the type constants are defined in axis.h |
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open function for spi support
This open is called from the general open after its worked out what type of subdevice user space has requested Open an individual SPI device for sanities sake only allow a single open for each device |
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Gets data from the selected SPI and returns it to userland.
Called by kernel in response to a user application making a read call. Note the user buffer pointer is not a valid address from inside the kernel. Gets data from the SPI device and returns it to userland. |
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Called by kernel in response to a process closing a device.
Called by kernel if user application closes device. Release must decrement the open count to signal that the device has been finished with and that other processes can open it |
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Copies data from USER space and sends it to spi.
Copies data from USER space and sends it on to the SPI write code |
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process a single SPI operation
In the case of SPI we have to write dummy data out in order to perform a read given this SPI read and write operations are managed by this one function. Note the hardware supports multiple SPI devices using one interface. We allow single open for each device this means operations must be queued so access to the SPI hardware is serialised |
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turn off SPI
once we have finished with SPI disable it |
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Initialise a SPI channel structure.
Initialise the SPI channel structure, called as we initalise the PCI structure |
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reads SPI control register 1
Reads SPI control register 1 |
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Reads SPI status register.
Read status register associated with SPI device |
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set up SPI addressing for selected channel
The SPI hardware has multiple enable/chip select lines. These are set by writing a bit to a register. Note the PIC interface still needs this setting but the PIC select is used in the FPGA to gate the clock and data line. This was done to save pins |
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Writes optional SPI settings (bitorder divisor clock phase etc) to control register.
Writes optional SPI settings (bitorder divisor clock phase etc) to control register |
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writes SPI control register 2
The SPI control register handles error behaviour. I'm not sure if an SPI master should ever receive an over run error. Things must have gone badly wrong for this to occur. We clear the error just in case. This write only register overlays the SPI status register |
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moves spi operation on to queue for SPI hardware
While driver supports multiple SPI channels there is physically only one set of SPI hardware. Function implements queuing to prevent SPI concurrent operations from failing. |
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Initial value:
{
read: axis_spi_read,
write: axis_spi_write,
ioctl: axis_spi_ioctl,
open: axis_spi_open,
release: axis_spi_release,
}
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1.3.6