axis_hardware.h File Reference

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Detailed Description

Axis register offsets and bit definitions.

Author:

Andrew Roca

Provides definitions for register offset interrupt mask and other bit definitions associated with the Axis hardware

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/serial.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/mtd/mtd.h>
#include <linux/crypto.h>
#include <asm/uaccess.h>

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Defines
#define	AXIS_PCI_VENDOR_ID   0x10b5
	AXIS_PCI_VENDOR_ID The code embedded in the hardware that identifies the PCI device vendor.
#define	AXIS_PCI_DEVICE_ID   0x3001
	AXIS_PCI_DEVICE_ID The code embedded in the hardware that identifies the PCI device type.
#define	PLX_MEMORY_CONTROL_REGION   0
	PLX_MEMORY_CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines a memory mapped region allocated to the PLX control registers.
#define	PLX_IO_CONTROL_REGION   1
	PLX_IO_CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines a IO mapped region allocated to the PLX control registers.
#define	STATIC_RAM_REGION   2
	STATIC_RAM_REGION The PCI device is mapped into multiple regions each with its own properties defines SRAM region.
#define	IO_REGION   3
	IO_REGION The PCI device is mapped into multiple regions each with its own properties defines IO region.
#define	CONTROL_REGION   4
	CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines Control/DES region.
#define	CONTROL_OFFSET   0x800
	CONTROL_OFFSET The DES core buffers and control register both appear in the same region the control registers have an offset address.
#define	MAX_REGION   6
	MAX_REGION Maxiumum number of regios PCI supports first two are the PLX chip last is reserved for BOOT proms.
#define	MAX_AXIS_ROUTED_SERIAL_PORTS   4
	MAX_AXIS_ROUTED_SERIAL_PORTS The first four UARTs are routable.
#define	AXIS_MAX_UARTS   8
	AXIS_MAX_UARTS The system supports upto 8 uarts (2x quad 16550).
#define	FALSE   (0)
#define	TRUE   (1)
#define	INTERRUPT_CONTROL_REGISTER   0x4c
#define	INTERRUPT_SETUP   0x041
#define	TYPE(dev)   (MINOR(dev)>>4)
	TYPE Extracts type of hardware from device node minor number.
#define	NUM(dev)   (MINOR(dev)>>2 &0x3)
	NUM Extracts which Axis device from device node minor number.
#define	SUB_NUM(dev)   (MINOR(dev) &0x3)
	NUM Extracts a subdevice id from device node minor number.
#define	MAX_AXIS_REGIONS   5
	MAX_AXIS_REGIONS The last region is reserved for BOOT proms so ignore it.
#define	UART_0_INTERRUPT_MASK_BITS   ((1<<0)|(1<<1)|(1<<2)|(1<<3))
	UART_0_INTERRUPT_MASK_BITS the interrupts bits that first quad UART will generate.
#define	UART_1_INTERRUPT_MASK_BITS   ((1<<4)|(1<<5)|(1<<6)|(1<<7))
	UART_1_INTERRUPT_MASK_BITS the interrupts bits that second quad UART will generate.
#define	DESA_INTERRUPT_BIT   (1<<8)
	DESA_INTERRUPT_BIT DES Channel A interrupt bit.
#define	DESB_INTERRUPT_BIT   (1<<9)
	DESB_INTERRUPT_BIT DES Channel B interrupt bit.
#define	DESC_INTERRUPT_BIT   (1<<10)
	DESC_INTERRUPT_BIT DES Channel C interrupt bit.
#define	DESD_INTERRUPT_BIT   (1<<11)
	DESD_INTERRUPT_BIT DES Channel D interrupt bit.
#define	SPI_INTERRUPT   (1<<12)
	SPI_INTERRUPT spi interrupt (tx + rx orded).
#define	INPUTS_INTERRUPT   (1<<13)
	INPUTS_INTERRUPT interrupt on input change.
#define	OUTPUTS_INTERRUPT   (1<<14)
	OUTPUTS_INTERRUPT interrupt on ouput timer.
#define	SECURITY_FAIL_INTERRUPT   (1<<15)
#define	SECURITY_PASS_INTERRUPT   (1<<25)
#define	SECURITY_TIMEOUT_INTERRUPT   (1<<26)
#define	SECURITY_INTERRUPTS   (SECURITY_FAIL_INTERRUPT|SECURITY_PASS_INTERRUPT/*|SECURITY_TIMEOUT_INTERRUPT*/)
#define	SPI_WRITE_INTERRUPT   (1<<16)
#define	SPI_READ_INTERRUPT   (1<<17)
#define	SMART_RX_INTERRUPT   (1<<20)
#define	SMART_TX_INTERRUPT   (1<<21)
#define	SMART_FRAME_ERROR_INTERRUPT   (1<<22)
#define	SMART_PARITY_ERROR_INTERRUPT   (1<<23)
#define	PCI_TIMEOUT_INTERRUPT   (1<<24)
#define	DES_INTERRUPT_BITS   (DESA_INTERRUPT_BIT|DESB_INTERRUPT_BIT|DESC_INTERRUPT_BIT|DESD_INTERRUPT_BIT)
#define	UART_INTERRUPT_MASK_BITS   (UART_0_INTERRUPT_MASK_BITS|UART_1_INTERRUPT_MASK_BITS)
#define	UART_ROUTE_REGISTER_OFFSET   (0x10+CONTROL_OFFSET)
#define	AXIS_INTERRUPT_REGISTER   (0x18+CONTROL_OFFSET)
#define	AXIS_INTERRUPT_MASK_REGISTER   (0x1C+CONTROL_OFFSET)
#define	AXIS_SECURITY_TIMER_REGISTER   (0x38+CONTROL_OFFSET)
#define	AXIS_SECURITY_TIMER_MASK   0xFFFF
#define	AXIS_ID_AND_ISSUE_REG   (0xC+CONTROL_OFFSET)
#define	AXIS_ID_SHIFT   8
#define	AXIS_ID_MASK   0XFFFFFF
#define	AXIS_ISSUE_SHIFT   0
#define	AXIS_ISSUE_MASK   0XFF
#define	AXIS_MAX_SUB_DEVICES   40
Functions
void	timeval_less_local (struct timeval a, struct timeval b, struct timeval *result)
	Subtracts to timeval structures to give a difference.

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Define Documentation

#define AXIS_ID_AND_ISSUE_REG   (0xC+CONTROL_OFFSET)

#define AXIS_ID_MASK   0XFFFFFF

#define AXIS_ID_SHIFT   8

#define AXIS_INTERRUPT_MASK_REGISTER   (0x1C+CONTROL_OFFSET)

#define AXIS_INTERRUPT_REGISTER   (0x18+CONTROL_OFFSET)

#define AXIS_ISSUE_MASK   0XFF

#define AXIS_ISSUE_SHIFT   0

#define AXIS_MAX_SUB_DEVICES   40

#define AXIS_MAX_UARTS   8

AXIS_MAX_UARTS The system supports upto 8 uarts (2x quad 16550).

#define AXIS_PCI_DEVICE_ID   0x3001

AXIS_PCI_DEVICE_ID The code embedded in the hardware that identifies the PCI device type.

#define AXIS_PCI_VENDOR_ID   0x10b5

AXIS_PCI_VENDOR_ID The code embedded in the hardware that identifies the PCI device vendor.

#define AXIS_SECURITY_TIMER_MASK   0xFFFF

#define AXIS_SECURITY_TIMER_REGISTER   (0x38+CONTROL_OFFSET)

#define CONTROL_OFFSET   0x800

CONTROL_OFFSET The DES core buffers and control register both appear in the same region the control registers have an offset address.

#define CONTROL_REGION   4

CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines Control/DES region.

#define DES_INTERRUPT_BITS   (DESA_INTERRUPT_BIT|DESB_INTERRUPT_BIT|DESC_INTERRUPT_BIT|DESD_INTERRUPT_BIT)

#define DESA_INTERRUPT_BIT   (1<<8)

DESA_INTERRUPT_BIT DES Channel A interrupt bit.

#define DESB_INTERRUPT_BIT   (1<<9)

DESB_INTERRUPT_BIT DES Channel B interrupt bit.

#define DESC_INTERRUPT_BIT   (1<<10)

DESC_INTERRUPT_BIT DES Channel C interrupt bit.

#define DESD_INTERRUPT_BIT   (1<<11)

DESD_INTERRUPT_BIT DES Channel D interrupt bit.

#define FALSE   (0)

#define INPUTS_INTERRUPT   (1<<13)

INPUTS_INTERRUPT interrupt on input change.

#define INTERRUPT_CONTROL_REGISTER   0x4c

#define INTERRUPT_SETUP   0x041

#define IO_REGION   3

IO_REGION The PCI device is mapped into multiple regions each with its own properties defines IO region.

#define MAX_AXIS_REGIONS   5

MAX_AXIS_REGIONS The last region is reserved for BOOT proms so ignore it.

#define MAX_AXIS_ROUTED_SERIAL_PORTS   4

MAX_AXIS_ROUTED_SERIAL_PORTS The first four UARTs are routable.

#define MAX_REGION   6

MAX_REGION Maxiumum number of regios PCI supports first two are the PLX chip last is reserved for BOOT proms.

#define NUM (  dev   )     (MINOR(dev)>>2 &0x3)

NUM Extracts which Axis device from device node minor number.

#define OUTPUTS_INTERRUPT   (1<<14)

OUTPUTS_INTERRUPT interrupt on ouput timer.

#define PCI_TIMEOUT_INTERRUPT   (1<<24)

#define PLX_IO_CONTROL_REGION   1

PLX_IO_CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines a IO mapped region allocated to the PLX control registers.

#define PLX_MEMORY_CONTROL_REGION   0

PLX_MEMORY_CONTROL_REGION The PCI device is mapped into multiple regions each with its own properties defines a memory mapped region allocated to the PLX control registers.

#define SECURITY_FAIL_INTERRUPT   (1<<15)

#define SECURITY_INTERRUPTS   (SECURITY_FAIL_INTERRUPT|SECURITY_PASS_INTERRUPT/*|SECURITY_TIMEOUT_INTERRUPT*/)

#define SECURITY_PASS_INTERRUPT   (1<<25)

#define SECURITY_TIMEOUT_INTERRUPT   (1<<26)

#define SMART_FRAME_ERROR_INTERRUPT   (1<<22)

#define SMART_PARITY_ERROR_INTERRUPT   (1<<23)

#define SMART_RX_INTERRUPT   (1<<20)

#define SMART_TX_INTERRUPT   (1<<21)

#define SPI_INTERRUPT   (1<<12)

SPI_INTERRUPT spi interrupt (tx + rx orded).

#define SPI_READ_INTERRUPT   (1<<17)

#define SPI_WRITE_INTERRUPT   (1<<16)

#define STATIC_RAM_REGION   2

STATIC_RAM_REGION The PCI device is mapped into multiple regions each with its own properties defines SRAM region.

#define SUB_NUM (  dev   )     (MINOR(dev) &0x3)

NUM Extracts a subdevice id from device node minor number.

#define TRUE   (1)

#define TYPE (  dev   )     (MINOR(dev)>>4)

TYPE Extracts type of hardware from device node minor number.

#define UART_0_INTERRUPT_MASK_BITS   ((1<<0)|(1<<1)|(1<<2)|(1<<3))

UART_0_INTERRUPT_MASK_BITS the interrupts bits that first quad UART will generate.

#define UART_1_INTERRUPT_MASK_BITS   ((1<<4)|(1<<5)|(1<<6)|(1<<7))

UART_1_INTERRUPT_MASK_BITS the interrupts bits that second quad UART will generate.

#define UART_INTERRUPT_MASK_BITS   (UART_0_INTERRUPT_MASK_BITS|UART_1_INTERRUPT_MASK_BITS)

#define UART_ROUTE_REGISTER_OFFSET   (0x10+CONTROL_OFFSET)

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Function Documentation

void timeval_less_local (  struct timeval  a, struct timeval  b, struct timeval *  result )  [inline, static]

Subtracts to timeval structures to give a difference. Parameters: a  - first operand b  - value to subtract from first result  - pointer to final result Returns: NONE Subtracts to timeval structures to give a difference, allow an elaspsed time to be calculated from two times

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